/**************************************************************************//**
 * @file     startup_ARMCM0.S
 * @brief    CMSIS-Core(M) Device Startup File for Cortex-M0 Device
 * @version  V2.2.0
 * @date     26. May 2021
 ******************************************************************************/
/*
 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

                .syntax  unified
                .arch    armv6-m

                .section .vectors
                .align   2
                .globl   __Vectors
                .globl   __Vectors_End
                .globl   __Vectors_Size
__Vectors:
                .long    __StackTop                         /*     Top of Stack */
                .long    Reset_Handler                      /*     Reset Handler */
                .long    NMI_Handler                        /* -14 NMI Handler */
                .long    HardFault_Handler                  /* -13 Hard Fault Handler */
                .long    0                                  /*     Reserved */
                .long    0                                  /*     Reserved */
                .long    0                                  /*     Reserved */
                .long    0                                  /*     Reserved */
                .long    0                                  /*     Reserved */
                .long    0                                  /*     Reserved */
                .long    0                                  /*     Reserved */
                .long    SVC_Handler                        /*  -5 SVCall Handler */
                .long    0                                  /*     Reserved */
                .long    0                                  /*     Reserved */
                .long    PendSV_Handler                     /*  -2 PendSV Handler */
                .long    SysTick_Handler                    /*  -1 SysTick Handler */

                /* Interrupts */
                .long    TIMER0_IRQHandler                 /*   0 Interrupt  0 */
                .long    TIMER1_IRQHandler                 /*   1 Interrupt  1 */
                .long    TIMER2_IRQHandler                 /*   2 Interrupt  2 */
                .long    Interrupt3_Handler                 /*   3 Interrupt  3 */
                .long    QEP0_IRQHandler                 /*   4 Interrupt  4 */
                .long    Interrupt5_Handler                 /*   5 Interrupt  5 */
                .long    I2C0_IRQHandler                 /*   6 Interrupt  6 */
                .long    SPI0_IRQHandler                 /*   7 Interrupt  7 */
                .long    GPIO_IRQHandler                 /*   8 Interrupt  8 */
                .long    HALL0_IRQHandler                 /*   9 Interrupt  9 */
                .long    UART0_IRQHandler                /*  10 Interrupt 10 */
                .long    UART1_IRQHandler                /*  11 Interrupt 11 */
                .long    UART2_IRQHandler                /*  12 Interrupt 12 */
                .long    CMP_IRQHandler                /*  13 Interrupt 13 */
                .long    ADC0_IRQHandler                /*  14 Interrupt 14 */
                .long    ADC1_IRQHandler                /*  15 Interrupt 15 */
                .long    MCPWM0_IRQHandler                /*  16 Interrupt 16 */
                .long    MCPWM1_IRQHandler                /*  17 Interrupt 17 */
                .long    DMA0_IRQHandler                /*  18 Interrupt 18 */
                .long    Interrupt19_Handler                /*  19 Interrupt 19 */
                .long    SIF0_IRQHandler                /*  20 Interrupt 20 */
                .long    WAKE_IRQHandler                /*  21 Interrupt 21 */
                .long    SW_IRQHandler                /*  22 Interrupt 22 */
                .long    PWRDN_IRQHandler                /*  23 Interrupt 23 */
                .long    CL0_IRQHandler                /*  24 Interrupt 24 */
                .long    DSP0_IRQHandler                /*  25 Interrupt 25 */
                .long    Interrupt26_Handler                /*  26 Interrupt 26 */
                .long    Interrupt27_Handler                /*  27 Interrupt 27 */
                .long    Interrupt28_Handler                /*  28 Interrupt 28 */
                .long    Interrupt29_Handler                /*  29 Interrupt 29 */
                .long    Interrupt30_Handler                /*  30 Interrupt 30 */
                .long    Interrupt31_Handler                /*  31 Interrupt 31 */

__Vectors_End:
                .equ     __Vectors_Size, __Vectors_End - __Vectors
                .size    __Vectors, . - __Vectors


                .thumb
                .section .text
                .align   2

                .thumb_func
                .type    Reset_Handler, %function
                .globl   Reset_Handler
                .fnstart
Reset_Handler:
                bl       SystemInit

                ldr      r4, =__copy_table_start__
                ldr      r5, =__copy_table_end__

.L_loop0:
                cmp      r4, r5
                bge      .L_loop0_done
                ldr      r1, [r4]                /* source address */
                ldr      r2, [r4, #4]            /* destination address */
                ldr      r3, [r4, #8]            /* word count */
                lsls     r3, r3, #2              /* byte count */

.L_loop0_0:
                subs     r3, #4                  /* decrement byte count */
                blt      .L_loop0_0_done
                ldr      r0, [r1, r3]
                str      r0, [r2, r3]
                b        .L_loop0_0

.L_loop0_0_done:
                adds     r4, #12
                b        .L_loop0

.L_loop0_done:

                ldr      r3, =__zero_table_start__
                ldr      r4, =__zero_table_end__

.L_loop2:
                cmp      r3, r4
                bge      .L_loop2_done
                ldr      r1, [r3]                /* destination address */
                ldr      r2, [r3, #4]            /* word count */
                lsls     r2, r2, #2              /* byte count */
                movs     r0, 0

.L_loop2_0:
                subs     r2, #4                  /* decrement byte count */
                blt      .L_loop2_0_done
                str      r0, [r1, r2]
                b        .L_loop2_0
.L_loop2_0_done:

                adds     r3, #8
                b        .L_loop2
.L_loop2_done:

                bl       _start

                .fnend
                .size    Reset_Handler, . - Reset_Handler

/* The default macro is not used for HardFault_Handler
 * because this results in a poor debug illusion.
 */
                .thumb_func
                .type    HardFault_Handler, %function
                .weak    HardFault_Handler
                .fnstart
HardFault_Handler:
                b        .
                .fnend
                .size    HardFault_Handler, . - HardFault_Handler

                .thumb_func
                .type    Default_Handler, %function
                .weak    Default_Handler
                .fnstart
Default_Handler:
                b        .
                .fnend
                .size    Default_Handler, . - Default_Handler

/* Macro to define default exception/interrupt handlers.
 * Default handler are weak symbols with an endless loop.
 * They can be overwritten by real handlers.
 */
                .macro   Set_Default_Handler  Handler_Name
                .weak    \Handler_Name
                .set     \Handler_Name, Default_Handler
                .endm


/* Default exception/interrupt handler */

                Set_Default_Handler  NMI_Handler
                Set_Default_Handler  SVC_Handler
                Set_Default_Handler  PendSV_Handler
                Set_Default_Handler  SysTick_Handler

                Set_Default_Handler  TIMER0_IRQHandler        
                Set_Default_Handler  TIMER1_IRQHandler        
                Set_Default_Handler  TIMER2_IRQHandler        
                Set_Default_Handler  Interrupt3_Handler       
                Set_Default_Handler  QEP0_IRQHandler          
                Set_Default_Handler  Interrupt5_Handler       
                Set_Default_Handler  I2C0_IRQHandler          
                Set_Default_Handler  SPI0_IRQHandler          
                Set_Default_Handler  GPIO_IRQHandler          
                Set_Default_Handler  HALL0_IRQHandler         
                Set_Default_Handler  UART0_IRQHandler         
                Set_Default_Handler  UART1_IRQHandler         
                Set_Default_Handler  UART2_IRQHandler         
                Set_Default_Handler  CMP_IRQHandler           
                Set_Default_Handler  ADC0_IRQHandler          
                Set_Default_Handler  ADC1_IRQHandler          
                Set_Default_Handler  MCPWM0_IRQHandler        
                Set_Default_Handler  MCPWM1_IRQHandler        
                Set_Default_Handler  DMA0_IRQHandler          
                Set_Default_Handler  Interrupt19_Handler      
                Set_Default_Handler  SIF0_IRQHandler          
                Set_Default_Handler  WAKE_IRQHandler          
                Set_Default_Handler  SW_IRQHandler            
                Set_Default_Handler  PWRDN_IRQHandler         
                Set_Default_Handler  CL0_IRQHandler           
                Set_Default_Handler  DSP0_IRQHandler          
                Set_Default_Handler  Interrupt26_Handler      
                Set_Default_Handler  Interrupt27_Handler      
                Set_Default_Handler  Interrupt28_Handler      
                Set_Default_Handler  Interrupt29_Handler      
                Set_Default_Handler  Interrupt30_Handler      
                Set_Default_Handler  Interrupt31_Handler      

                .end
